Floorplan considering interconnection between different clock domains

نویسندگان

  • Linkai Wang
  • Xiaofang Zhou
چکیده

A further research on floorplanning considering multi clock domains is presented in this paper, which concentrates on interconnection between different clock domains. This contributes to simplification of clock tree and signal routing between different clock domains. Experimental results show that better floorplan can be obtained through our floorplanning proposed in this paper. Key-Words: Floorplan Clock domain Interconnection Physical design

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Microarchitecture Level Interconnect Modeling Considering Layout Optimization

— In this paper, we study microarchitecture-level interconnect modeling for power and performance. Considering structural interconnects, layer assignment, and concurrent repeater and Flip-Flop (FF) insertion, we develop cycle-accurate microarchitecture-level power and throughput simulation and obtain an accurate modeling of interconnects at the early design stage. Experiment show that the simul...

متن کامل

A Survey on Floorplan Representations in VLSI

In the state of the art of computer designing interconnection of a huge number of circuit elements in a small enough area possess a challenge for the designers. This is possible if the task is divided into smaller independent modules. This is helpful for concurrent design of the individual modules as well. Interestingly the suitable placement and proper interconnection of these modules became a...

متن کامل

Exploiting Non-Uniform Access Time in Interconnect Sensitive Cache Partitioning

Growing wire delay and clock rates limit the amount of cache accessible within a single cycle [3,13]. Cache architectures assume that each level in the cache hierarchy require a uniform access time. As microprocessor technology advance, architects must decide how to best utilize increased resources while accounting for growing wire delays and clock rates. Because on-chip communication is very c...

متن کامل

A Heuristic Approach for VLSI Floorplanning

Floorplanning is an essential step in VLSI chip design automation. The main objective of the floorplanning is to find a floorplan such that the cost is minimized. This is achieved by minimizing the chip area and interconnection cost. It determines the performance, size, yield and reliability of VLSI chips. We propose a Memetic Algorithm (MA) for non-slicing and hard module VLSI floorplanning pr...

متن کامل

Hierarchical and Multiple Switching NoC with Floorplan Based Adaptability

The Networks-on-Chip paradigm has been seen as an interconnect architecture solution for complex systems. However, performance and energy issues still represent limiting factors for Multi-Processors System-on-Chip. Moreover, the execution of different applications requires flexible and transparent interconnection solutions, and this feature is best provided by a selfadaptable system. In this pa...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 2007